Sequential generations of computing systems typically require higher degrees of performance and feature integration. A typical computing system includes a central processing unit (CPU), a graphics processing unit (GPU), a high-capacity memory subsystem, and set of interface subsystems. The interface subsystems may include audio and video interfaces, signal processing blocks, a digital modem block, a wireless communications block, and the like. Conventional computing systems achieve higher degrees of performance and integration by implementing one or more CPU cores, one or more GPU cores, and a set of feature-specific subsystems, such as interface blocks, on a single die or chip. Such highly integrated chips are referred to in the art as a system-on-a-chip (SoC). Measures of die area for SoC devices have increased over time, as more CPU cores, GPU cores, on-chip cache memory, and additional interface blocks are integrated into a single SoC die. One advantage of integrating multiple processing cores and interface subsystems onto a single die is that high-performance may be achieved using conventional design techniques.
However, one disadvantage of integrating multiple processing cores and other subsystems onto a single SoC die is that die cost can increase disproportionately with respect to die area. More specifically, die area is typically a strong function of die area, which, in many cases, increases above a characteristic cost knee, leading to disproportionate cost inefficiencies associated with very large die. However, conventional chip-to-chip signaling techniques do not efficiently support multiprocessing performance targets commonly associated with high-performance SoC devices. As a consequence, only wide, on-chip interconnects are conventionally feasible options to achieve overall system performance targets.
One disadvantage of integrating certain feature-specific subsystems onto a given SoC device is that performance of a feature-specific subsystem may be compromised by a particular die fabrication process that may be optimized for other SoC subsystems, such as CPU and GPU processing cores. For example, a feature-specific subsystem implementing a digital radio modem comprising a mix of analog and digital circuit elements may require very different device characteristics for optimal performance than a CPU core comprising only digital circuit elements. In this example, selecting a die fabrication process optimized for the CPU core may lead to compromised performance of the digital radio modem.
Thus, there is a need for improving signaling and/or other issues associated with the prior art.